1. Field of the Invention
This invention relates generally to an information processing device for use in personal computers, workstations, etc., and more particularly to a system for controlling the frequency operation or execution time of a bus cycle to be executed by the central processing unit (CPU) of an information processing device.
2. Description of Related Art
The recent progress in the techniques for increasing the operational rate of CPUs, dynamic random access memories (DRAMs), and erasable programmable read only memories (EPROM) has been phenomenal. Accompanying this progress, makers of personal computers have annually developed and marketed new products with improved processing rates. The clock frequency of the CPU is substantially increased and DRAMs, EPROMs or such memory units are employed as high speed memory for improving performance. However, although the CPU and memory speed have been significantly improved, the operational speed of Input/Output (I/O) devices and units employed in conjunction with such CPUs have not been correspondingly increased. Accordingly, when the clock frequency of the CPU is increased, the operational speed of associated CPU memory is as high as that of the CPU. However, the associated I/O device cannot operate at the processing speed of the CPU. As a result, some means is necessary for solving this problem.
Conventionally, this problem has been dealt with by employing the READY terminal of the CPU to cause the CPU to wait for the slower execution action of the I/O device, i.e. when the CPU accesses the I/O device, the I/O device inactivates the READY signal in order to cause the CPU to wait while the I/O devices completes the execution of instructions. As a result, the high speed CPU and the low speed I/O device are operationally congruent with one another.
The foregoing conventional method is now explained by means of the following examples. FIGS. 35 and 36 are explanatory views of a referenced information processing device. This referenced information processing device has been set up for the purpose of clarifying the differences between the invention of this application and the conventional art. The parts of the information processing device which are not directly relevant to this invention have been much simplified or omitted since they are not necessary to the explanation of this invention. Accordingly, the referenced information processing device is a little unnatural compared with the conventional information processing device but is illustrated as such because of the convenience and clarity it brings in understanding the invention of this application. The conventional method of increasing the processing or operational speed of the referenced information processing device is illustrated in FIGS. 35 and 36.
FIG. 31 illustrates a referenced information processing device. FIG. 32 is a timing diagram illustrating the operation of the information processing device of FIG. 31. In FIG. 31, CPU 21 is an 8 MHz version of the INTEL 80286. Relative to the terminals of CPU 21, CLK represents a clock input terminal and is supplied with a frequency twice an operational speed of CPU 21. Three signals, M/ IO, SI, SO are state discrimination signals representing the state of a bus cycle of CPU 21. These signals indicate the states set forth in Table 1 below. In Table 1, the corresponding signals are only those relevant to the description of this application.
TABLE 1 ______________________________________ ##STR1## ##STR2## ##STR3## Bus Cycle Corresponding Signals ______________________________________ 0 0 0 Interrupt Acknowledge 0 0 1 I/O Read ##STR4## 0 1 0 I/O Write ##STR5## 0 1 1 None (Idle) Hold or Shutdown 1 0 1 Memory Read ##STR6## 1 0 1 Memory Read ##STR7## 1 1 1 None (Idle) ______________________________________
Table 1 illustrates the correspondence between the bus cycles respectively with M/IO, SI, and SO. READY represents a ready terminal. When the signal at the ready terminal is high, extended bus cycles are activated into operation and when the signal is low, the bus cycles are terminated. In FIG. 31, for simplifying the explanation, READY is set low. A23-A0 are address buses. D15-D0 are data buses. A command decode circuit 2 produces command signals MEMR, MEMW, IOR, IOW) corresponding to the state discrimination signals M/IO, SI, SO indicative of the states of the bus cycles. The output of an oscillation circuit 23 is 16 MHz which is the clock signal for CPU 21.
FIG. 32 illustrates the timing relationships among the respective signals in the circuit of FIG. 31 and the timing diagram of four bus cycles executed by CPU 21. T31 represents the memory read bus cycle; T32, the I/O read bus cycle; T33, the memory write bus cycle; and T34, the I/O write bus cycle. Each of the bus cycles comprises two clock cycles TS and TC. Each of the clock cycles comprises two CLK pulses. Each of the CLK pulses has a frequency of 16 MHz, and the period of each cycle TS, TC is 125 ns (f/sec.). The period of each of the four bus cycles T31, T32, T33 and T34 is 250 ns. CPU 21 outputs the state discrimination signals M/IO, SI, and SO to discriminate relative to the respective bus cycles. Command decode circuit 2 decodes these state discrimination signals into corresponding command signals, i.e., MEMR relative to the bus cycle T31, IOR relative to the bus cycle T32, MEMW relative to the bus cycle T33, and IOW relative to the bus cycle T34. Each signal MEMR, IOR, MEMW and IOW has a pulse width of 125 ns.
FIG. 33 is a block diagram of the conventional method employed in connection with a referenced information device for providing an increase in the processing speed of a referenced information device shown in FIG. 31. In FIG. 33 CPU 201 is a 12 MHz version product of the INTEL 80826. Oscillation circuit 213 has an output pulse of a higher frequency comprising 24 MHz. When the clock frequency of CPU 201 is increased from 16 MHz to 24 MHz relative to the circuit of FIG. 31, the periods of the respective bus cycles (T31-T34) in FIG. 32 change from 250 ns to 167 ns, i.e., the cycle periods are shortened by approximately 33%. The memory read bus cycle and the memory write bus cycle can be executed in a period of 167 ns without any difficulty by employing a high speed memory. It is difficult, however, to operate an I/O device in 167 ns period because the processing speed of the I/O device has not been improved like that of memory units and substantially the same I/O bus cycle period as found in the referenced information processing device of FIGS. 31 and 32 is required. As a result, it is necessary to use the READY signal to provide an extended wait period for the execution of the I/O read bus cycle and I/O write bus cycle. READY control circuit 216 provides this extended wait function for the I/O bus cycle. No wait is necessary for the memory bus cycles. Command decoder circuit 212 in FIG. 33 also has the function of extending the pulse of the IOR and the IOW signals during a wait period in addition to the function of the command decoder previously described in connection with FIG. 31.
FIG. 34 is a flow diagram of the timing relationships among the respective signals in the circuit of FIG. 33. As in FIG. 32, the timing diagram of four bus cycles are shown. Each CLK pulse has a frequency of 24 MHz, and the period of each of clock cycles TS and TC is 83 ns. The period of each memory read bus cycle T21 and memory write cycle T23, which are provided with no wait, is 167 ns. In contrast to this, each I/O bus read bus cycle T22 and I/O write bus cycle T24, which are provided one wait in accordance with a wait signal, comprises three clock cycles TS, TC and TC, i.e., the periods of these bus cycles are 250 ns and are the same as those of bus cycles T32 and T34. An IOR signal and an IOW signal in bus cycles T22 and T24 are the most active among the inserted clock cycles TC and have a pulse width of 167 ns.
In the referenced information processing device of FIGS. 33 and 34, the READY signal is causes CPU 201 to wait in order to extend the bus cycles to thereby adjust the operational speed of a slower I/O device. Conventionally this method has caused substantially no problems. However, recently there have occurred situations indicating that this method is not perfect and is undesirable. Recently, personal computers have been progressively standardized. The specifications of especially the so called option slots, the connectors for expansion boards, have been fairly standardized. The option slots are connectors provided in personal computers for receiving expansion boards optionally used by users when they need functions in addition to those basically provided by personal computers manufactures. The expansion boards are supplied in a wide variety of types and kinds by personal computer manufacturers themselves and also by special expansion board third party vendors. Thus, expansion boards for the personal computers are becoming more and more important. Accordingly when personal computer manufactures merchandise new products, they are forced to design them beforehand so that a number of expansion boards produced for already marketed products can also operate on these new products.
The following assumptions are made relative to the circuits of FIGS. 31 and 33. The circuit of FIG. 31 is an already marketed product and the circuit of FIG. 33 is a new product and the I/O read bus cycle and the I/O write bus cycle are the bus cycles on an expansion board to be connected to the option slot provided in these information processing. devices. Further, it is assumed that an expansion board has been designed for an already marketed product, i.e., it is assumed that the expansion board has been designed so that the respective signals have the timings of the bus cycles T32 and T34 in FIG. 32. But each of bus cycles T22, T24 in FIG. 34 are given one wait to agree with the bus cycles T32, T34 only in the bus cycle period but differ from the bus cycles T32, T34 in other points. Compared with only the bus cycle T24, the pulse width of an IOW signal, for example, is different from that of the bus cycle T34, i.e., the pulse width of the bus cycle T34 is 125 ns, but that of the bus cycle T24 is 167 ns. The setup time and the hold time for data to be written via D15-DO for the IOW signal are different from those of the bus cycle T34. Thus, some expansion boards will not operate in connection with a new product based upon the operation of circuit of FIG. 33.
On the other hand, a microprocessor will be discussed from a viewpoint other than that from which has been discussed the information processing device.
The clock frequency of the microprocessor has been increased year by year in conjunction with the progress of semiconductor high speed digital design and fabrication. The information processing device manufacturers have also realized and now appreciate the importance of compatibility among their products, i.e., when an information processing device manufacturer merchandises a new version or product of their already marketed product, they take into consideration third party vendor application software and hardware, such as option boards, which already functionally operate with their marketed product, to provide their compatibility with their new version. The most common means to provide for this compatibility is to provide two frequencies is the same as that of the microprocessor of the old product and the other is the maximum operational clock frequency of the microprocessor of the new version or product. For example, in the case where the clock frequency of the microprocessor of the old product is 6 MHz, and that of the new product is 12 MHz, the new product has two clock frequencies of 6 MHz and 12 MHz, and operation is switched between these frequencies, e.g., by a switch. Usually new products are operated at the clock frequency of 12 MHz, but when an application program for the old product does not operate properly at the higher frequency of the new product due to a difference in processing speed, the clock frequency is switched to 6 MHz. Thus, the compatibility between the old and the new products can be assured by this approach. Thus, relative to these circumstances, the clock frequency switching circuit of the microprocessor has become an important function.
FIG. 35A is an example of a conventional clock frequency switching circuit for switching clock frequencies of microprocessor 1, such as an INTEL 80C286. The maximum clock input frequency is 24 MHz. This 80C286 microprocessor requires a clock of a frequency twice the internal operational speed and the microprocessor having the maximum clock input frequency of 24 MHz is called a CPU 12 MHz version. Oscillation circuit 306 provides an output frequency signal of 48 MHz called CLKI. A switch 305 provides the switching operation for the clock frequency of CPU 1. When switch 305 is in its lower position, signal S is of low level (L). When switch 305 is in its higher position, signal S is of high level (H). Flip flop (FF) 312 synchronizes signal S to produce a signal C.sub.A. Frequency dividing circuit 307 functions as a frequency bisecting circuit when the signal C.sub.A is L. When signal C.sub.A is H, circuit 307 functions as a frequency quartering circuit. Frequency dividing circuit 307 comprises two FFs. When their Q outputs are represented by Q.sub.A and Q.sub.B respectively, with C.sub.A =L, (Q.sub.A,Q.sub.B) changes from (0,0) to (1,1) and to (0,0), and with C.sub.A =H, (Q.sub.A,Q.sub.B) changes from (0,0) to (1,0), to (1,1), to (0,1) and to (0,0). This state transition is illustrated in FIG. 35C.
With reference to the general operation of the conventional information processing device of FIG. 35A, when the switch 305 is in its lower position, C.sub.A =L, frequency dividing circuit 307 functions as a frequency bisecting circuit. As a result, the frequency of the CLKO signal for CPU 1 is 24 MHz as compared to the frequency of 48 MHz of the CLKI signal to circuit 307. When switch 305 is in its higher position, C.sub.A =H, and frequency dividing circuit 307 functions as a frequency quartering circuit. As a result, the frequency of the CLKO signal is 12 MHz, i.e., frequency dividing circuit 307 in FIG. 35A switches the frequency between 24 MHz and 12 MHz to supply designated clock pulses to the CPU clock terminal. Here, as shown in FIG. 35B, C.sub.A =0 means the same as C.sub.A =L, and C.sub.A =1 means the same as C.sub.A =H. FIG. 35C is state transition diagram for the circuit of FIG. 35A. FIG. 35D illustrates the timing relationship relative to signals CLKI, S, C.sub.A, Q.sub.A and CLKO.
FIG. 36 is another conventional method for switching between different frequencies of operation. In this conventional method, respective outputs CLKI 1 and CLKI 2 from two different oscillation circuits 316, 326 are switched by clock switching circuit 317 to supply either of these clock frequencies as an output, CLKO. Oscillation circuit 316 provides an output frequency of 24 MHz and oscillation circuit 326 provides an output frequency of 12 MHz. Oscillation circuits 316, 326 oscillate independently of each other and are not synchronized. Accordingly, there is a danger that pulses of a narrow width are provided as an output, CLKO, when the clock rate is switched. Clock switching circuit 317 is, therefore, provided with a device to prevent the output of pulses not having the required specifications.
Thus, in the conventional approach provided in FIG. 35A, the oscillation circuit having a frequency as high as 48 MHz for original maximum oscillation is necessary in order to supply to CPU clock rates of 24 MHz and 12 MHz but comes at the expense of providing improper waveforms, particularly with narrower pulse shapes. In the conventional method of FIG. 36, two oscillation circuits are necessary but with a lower original maximum oscillation frequency compared to FIG. 35A. However, there is also the disadvantage of producing improper clock waveforms for the CPU. In addition, the costs of these circuits are high. Furthermore, clock switching circuit 317 is complicated, because two different unsynchronized two clock signals (CLKI 1, CLKI 2) are being switched.
Its a primary object of this invention to provide for dynamic or on-the-fly changing of bus cycle timing for a CPU in an information processing device in accordance with required changes in the clock frequency of operation of the CPU.
Another object of this invention is to provide a method for increasing the clock frequency of a CPU in the product design of new information processing devices which have been designed with higher operational frequencies to be compatible with higher frequencies of certain I/O devices, such as high speed memories, with shortened bus cycles thereby increasing the overall processing speed of the new product, while providing for compatibility with the timing relationships of clock dependent operational signals and cycles of such a new product with those of an older such product without limiting the operational frequency exclusively to the time periods for bus cycles required for timing compatibility for older applications provided via the device option slot, e.g., those corresponding to the I/O read bus cycle and the I/O write bus cycle of the conventional type and explained with reference to FIGS. 31-34.
Another object of this invention is to provide an information processing device with an innovative clock circuit which successfully provides for reduced costs over the frequency switching solutions of the prior art of FIGS. 35 and 36 while solving problems encountered in the prior art in providing the correct clocking signal waveform and frequency.